ASIC Front-End Verification Engineer at HPE | Bengaluru

About the Company

Hewlett Packard Enterprise (HPE) is a global edge-to-cloud company that helps organizations connect, protect, analyze, and act on their data and applications wherever they reside, from edge to cloud. The company focuses on helping businesses turn insights into outcomes quickly in a complex digital environment.

HPE values diverse backgrounds and encourages innovation, teamwork, and open communication. Employees are supported with flexibility and opportunities to grow while contributing to meaningful technological progress.

Job Overview

This position is designed as an onsite role, with work primarily performed from an HPE office. The engineer will contribute to the design and verification of VLSI components and hardware systems, including architecture analysis, logic design validation, and simulation-driven verification.

The role involves developing verification environments, analyzing design behavior, and supporting prototype and production VLSI solutions through rigorous testing and evaluation.

Key Responsibilities

• Work with modern verification methodologies such as UVM and support complex feature verification suites.
• Design and develop block-level verification environments for subsystems and full-chip designs using SystemVerilog and UVM methodology.
• Define, architect, code, and deliver verification suites and test cases for ASIC designs using front-end simulators such as VCS or NC.
• Independently verify large ASIC blocks and complete sign-off for tape-out through analysis of code coverage, functional coverage, and gate-level simulations.
• Collaborate with logic designers to identify and resolve design issues and assist software teams during bring-up and development phases.
• Create Perl, Python, or shell scripts to enhance verification infrastructure and automation.

Required Skills and Qualifications

• Experience with ASIC verification using SystemVerilog.
• Knowledge of constrained-random verification techniques.
• Familiarity with verification methodologies such as OVM, VMM, or UVM.
• Experience with scripting languages such as Perl or Tcl.
• Exposure to verification of networking protocols like Ethernet is desirable.
• Strong debugging ability and understanding of ASIC verification flows.
• BSEE or MSEE degree required.

Work Environment

Engineers in this role collaborate with global system design teams and contribute within a culture that emphasizes empowerment, teamwork, innovation, and performance-driven results. The position offers opportunities to expand technical expertise and work on advanced semiconductor technologies.