Cisco Bangalore Hiring ASIC Engineer (New Grad) | Freshers Eligible

Come join the Cisco Silicon One team and take part in the design and verification of leading-edge multimillion gate ASICs. Cisco Silicon One is an industry-leading networking silicon used across Cisco's core products. These chips power high-density, high-speed multi-protocol switches and routers for next-generation AI networking infrastructure, datacenters, campus and service provider networks.

Your Impact

You will join the creative Physical Design team in Bangalore, India, building next-generation networking chips on advanced process nodes. You will drive the backend flow through the full RTL2GDS implementation, including hierarchical floorplanning, place and route, timing closure, power integrity, static timing verification, physical verification and equivalence checks, with a focus on performance and die size optimization.

ASIC Physical Design Engineer

Join the physical design team on leading-edge multimillion gate ASICs using sub 5/3/2 nm technologies. If you enjoy solving complex technical challenges and want to build the silicon behind Cisco's global networking products, this role is for you.

ASIC Design and Verification Engineer

Join the team designing and verifying leading-edge multimillion gate ASICs. If you enjoy complex technical challenges and want to build the silicon behind Cisco's global networking products, this role is for you.

What You'll Bring

• Eligibility: The requirement is for 2027 graduates only.
• Project Management: Ability to manage multiple tasks and work toward long-term goals.
• Engineering Fundamentals: Solid understanding of engineering fundamentals, digital design fundamentals, and technical problem-solving skills.
• Collaboration: Experience establishing and sustaining strong relationships with the extended team.
• Communication: Excellent verbal and written communication skills.
• PD Knowledge: A strong grasp of digital design, CMOS technology, VLSI principles, timing and power fundamentals. Comfort with the complete RTL to GDSII flow, including logic synthesis, floorplanning, placement, clock tree synthesis, routing, static timing analysis and physical verification signoff. Understanding of setup and hold timing, clock skew, congestion, IR drop, electromigration, DRC, LVS, PVT corners and SDC constraints. Solid scripting skills for automating workflows.
• Design/Verification Knowledge: Knowledge of hardware design and test/verification environments built on an object-oriented framework in UVM, with coursework in advanced data structures, algorithms and design patterns, along with SystemVerilog HDL, C, C++ and Python.

Team players with a can-do attitude work well in a group and contribute individually. You will thrive here if you enjoy being challenged, learning new ideas and pushing toward aggressive technology goals.

Why Cisco?

At Cisco, we are revolutionizing how data and infrastructure connect and protect organizations in the AI era and beyond. We have been innovating for 40 years to create solutions that power how people and technology work together across physical and digital worlds.

Our worldwide network of experts gives you room to grow and build. We collaborate with empathy to make big things happen on a global scale. We are Cisco, and our power starts with you.

Disclaimer

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