NVIDIA Hiring ASIC Engineer New College Graduate 2026 | India

Physical Design Team

The Physical Design team drives end to end chip implementation from RTL to GDS. Work includes floor planning, place and route, timing closure, and physical verification while collaborating closely with design teams to optimize power, performance, and area across GPU and ASIC platforms.

• Work on block and chip level physical design activities.
• Perform floor planning, abstract view generation, RC extraction, PNR, STA, EM, IR drop analysis, DRC checks, and schematic to layout verification.
• Partner with design teams to resolve design challenges and debug tool or design related issues.
• Improve RTL to GDS flows to enhance performance, power, and area metrics.
• Support implementation of GPU and ASIC products across desktop, laptop, workstation, and mobile markets.

Timing Team

The ASIC Physical Design timing team designs and validates high performance ASICs for large scale silicon and chiplet based architectures. The focus is on delivering reliable timing closure while meeting performance and efficiency targets at advanced technology nodes.

• Drive full chip or chiplet level Static Timing Analysis from early design stages through timing sign off.
• Lead timing convergence across multiple partitions in multi mode multi corner environments.
• Contribute to top level floorplanning, clock architecture definition, and timing budgeting.
• Develop and maintain timing constraints across functional and test modes.
• Collaborate with RTL, PnR, and DFT teams to resolve timing bottlenecks and improve timing QoR.
• Enhance timing methodologies, automation, and sign off flows.

DFX Team

The Design for Test team develops solutions for DFT architecture, verification, and post silicon validation on complex semiconductor chips.

• Verify Memory BIST logic and DFT circuits including JTAG, IO BIST, and ATPG.
• Create scalable test plans for unit level and SoC or full chip verification using UVM and internal tools.
• Perform pre silicon simulation, debugging, and sign off on test coverage.
• Work on automation, coverage metrics, test execution, bug identification and fixes, and memory test productization.
• Collaborate with design and QA teams to improve test coverage and software quality.

PSSG Team

The Applied Power Architecture team develops power features and models that improve chip efficiency across consumer, server, mobile, and automotive platforms.

• Work with architecture, design, and validation teams to bring up and characterize power management features.
• Correlate silicon KPIs with pre silicon expectations.
• Collaborate with hardware and software teams to optimize silicon power and performance per watt.
• Create test plans and experiments to evaluate power behavior.
• Collect and analyze silicon power data for future chip power estimation models.

Circuit Design Team