Intel Hiring Physical Design Engineer in Bangalore | Apply

Job Description

Intel's HIPD - SAM group is seeking a Physical Design Engineer to contribute to high-speed mixed-signal IP designs used across Intel's server, client, and graphics microprocessors. In this role, you will work alongside architects, logic designers, and analog engineers to implement complex features from RTL through GDS. The work supports the development of advanced semiconductor technologies powering next-generation computing platforms.

Key Responsibilities

• Create and maintain a design database prepared for manufacturing with completed sign-off flows.
• Plan and analyze power supply networks and power grid structures to ensure reliable power delivery.
• Carry out logic synthesis, place-and-route, and clock tree synthesis using tools such as Synopsys and Cadence.
• Run verification tasks including formal equivalence verification (FEV), static timing analysis (STA), and physical verification checks such as LVS, DRC, and antenna validation.
• Optimize designs for improved power, frequency, and area while maintaining reliability.
• Perform power integrity analysis (IR/RV) and implement methods for reducing power consumption.
• Debug and resolve SoC-level integration issues in collaboration with cross-functional teams.
• Take part in design reviews and manage sign-off flows to prepare designs for manufacturing.
• Enhance physical design methodologies and support automation improvements in design flows.

Qualifications

Minimum Qualifications

• Bachelor's degree in Electrical Engineering or Electronics Engineering with 0-1+ years of relevant experience, or a Master's degree in Microelectronics or VLSI with no prior experience depending on business requirements.
• Hands-on knowledge of EDA tools including Synopsys Design Compiler, Cadence Innovus, and PrimeTime.
• Understanding of physical design methodologies and RTL-to-GDS implementation flows.
• Familiarity with static timing analysis, layout verification processes, and reliability verification techniques.

Preferred Qualifications

• Basic understanding of CMOS circuit design principles.
• Knowledge of digital logic optimization and trade-offs related to power, performance, and area.
• Experience with low-power implementation strategies and multi-power-domain analysis.
• Coursework or practical exposure to VLSI design and physical design flows.

Business Group

The Central Engineering Group (CEG) at Intel develops scalable engineering solutions across Product Enablement, Custom ASIC development, and Foundry Enablement. The team focuses on delivering customer-driven solutions with short development cycles that support Intel's product and foundry businesses.

Work Model

This position follows Intel's hybrid work model, allowing employees to divide their time between working on-site at the assigned Intel location and working remotely.