Physical Design Layout Engineer at Intel, Bangalore | Fresher Eligible

Job Description:

As a Physical Design Engineer, you will focus on creating and optimizing chip designs at the physical level. You will be responsible for crafting elements such as cell, block-level semi-custom layouts, FUB-level floor plans, and performing schematic-to-layout verification to ensure design integrity. Your contributions will directly impact the development and execution of complex chip methodologies, enabling Intel to deliver cutting-edge technology to the marketplace.

Business Group:

This role is part of Intel's broader semiconductor engineering organization, which is dedicated to designing, developing, and verifying innovative chip technologies. The team focuses on advancing physical design methodologies, ensuring reliability, and optimizing chip performance while supporting Intel's mission to create world-class computing solutions.

Key Responsibilities:

• Develop and refine physical chip designs, including cell and block-level semi-custom layouts, FUB-level floor plans, abstract view generation, and schematic-to-layout verification.
• Conduct reliability verification, debug issues, and apply proactive intervention strategies to optimize chip performance.
• Utilize parasitic extraction, custom polygon editing, auto-place and route algorithms, floor planning, and full-chip assembly techniques to ensure design success.
• Collaborate across teams to troubleshoot complex design challenges and deliver high-quality solutions.
• Participate in the execution of project methodologies, flow developments, and verification processes.