NVIDIA Hiring ASIC Design and STA Engineer, Bengaluru India

NVIDIA has continually reinvented itself. The invention of the GPU accelerated the growth of PC gaming, transformed computer graphics, and advanced parallel computing. Today, rapid progress in artificial intelligence requires highly scalable and massively parallel computing power, an area where NVIDIA GPUs excel.

The company continues to evolve by tackling complex challenges and adapting to new opportunities. Employees work in a collaborative and supportive environment focused on amplifying human creativity and intelligence while building impactful technologies.

NVIDIA is seeking an ASIC Design and STA Engineer to join the Networking Silicon engineering team. The group develops high speed communication devices designed to deliver exceptional throughput and low latency for modern AI platforms. This role involves contributing to the design of large scale and innovative silicon chips within a technology focused environment.

Key Responsibilities

• Drive full chip or chiplet level static timing analysis (STA) convergence from early design stages through signoff.
• Participate in top level floorplanning and clock planning activities.
• Collaborate on optimization of CAD signoff flows and related methodologies.
• Integrate timing for digital partitions and analog IPs, provide feedback to physical design and RTL teams, and support timing closure.
• Work with logic design and DFT engineers to define constraints for different operating modes and improve runtime efficiency.

Requirements

• B.Sc. or M.Sc. in Electrical Engineering, Computer Engineering, or a related field.
• Strong academic background, candidates pursuing or completing B.Tech or M.Tech in Computer Science or Electronics and Communication are considered.
• Understanding of programming languages and processor or SoC architecture is advantageous.
• Good knowledge of digital design fundamentals.
• Ability to debug complex issues and collaborate effectively within engineering teams.
• Comfort working in a collaborative and technically focused environment.

You will join a team of engineers building advanced physical design solutions for next generation silicon. The role provides exposure to large scale chip development and collaboration with experienced engineers across the semiconductor design flow.