Intel Hiring Physical Design Engineer in Bangalore | VLSI

Job Description

Intel is looking for an entry level Physical Design Engineer for a time bound assignment supporting block level and chip level physical design execution on advanced technology nodes.

The engineer will contribute as an individual contributor under the guidance of senior Physical Design leads. Responsibilities include implementation, timing analysis, and physical design signoff activities to help meet project milestones.

Key Responsibilities

• Carry out block level and chip level physical design implementation tasks
• Perform floorplanning, placement, clock tree synthesis (CTS), and routing for assigned blocks
• Support Static Timing Analysis including setup, hold, and clock checks
• Run and evaluate physical design signoff checks
• Conduct DRC and LVS verification
• Perform EM/IR analysis and power integrity reliability checks
• Debug timing and physical violations and assist with closure under guidance from PD and STA leads
• Support ECO implementation and final signoff closure
• Follow established methodologies, flows, and project guidelines
• Deliver assigned work with focus on quality, schedule adherence, and disciplined execution

Minimum Qualifications

• Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related discipline
• 0 to 2 years of industry experience or strong academic exposure in VLSI Physical Design or Backend Design
• Understanding of physical design fundamentals including floorplanning, placement, CTS, and routing
• Knowledge of timing basics such as setup and hold analysis and clocking concepts
• Familiarity with physical design and timing analysis flows
• Ability to work independently while receiving technical guidance

Preferred Qualifications

• Hands on exposure to EDA tools such as ICC2, Innovus, PrimeTime, or similar platforms
• Academic projects or internship experience related to STA, EM/IR, or physical design signoff
• Scripting experience with Tcl, Python, or Perl
• Exposure to advanced technology nodes and low power design concepts

Business Group

The Central Engineering Group (CEG) is Intel's data driven organization that builds scalable engineering solutions across Product Enablement, Custom ASIC, and Foundry Enablement. The group focuses on customer driven, end to end solutions with shorter development cycles that deliver measurable impact across Intel's product and foundry businesses.

Work Model

This position follows a hybrid work model, allowing employees to divide their time between working at the assigned Intel site and working off site.