Intel Hiring Physical Design Engineer in Bangalore | VLSI

Job Description

Intel is looking for an entry level Physical Design Engineer for a time bound assignment supporting block level and chip level physical design activities on advanced technology nodes.

The engineer will contribute as an individual contributor while working under the guidance of senior physical design leads. Responsibilities include implementation, timing analysis, and physical design signoff tasks to help meet project execution milestones.

Qualifications

• Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related discipline.
• 0 to 2 years of industry experience or strong academic exposure in VLSI Physical Design or Backend Design.
• Good understanding of physical design fundamentals including floorplanning, placement, clock tree synthesis (CTS), and routing.
• Knowledge of timing concepts such as setup and hold checks and clocking fundamentals.
• Familiarity with physical design and timing analysis flows.
• Ability to work independently as an individual contributor under technical guidance.
• Strong analytical thinking and problem solving ability with a willingness to learn.

Business Group

The Central Engineering Group (CEG) is Intel's data driven engineering organization that develops scalable solutions across three key areas: Product Enablement, Custom ASIC development, and Foundry Enablement. The team focuses on delivering customer driven end to end solutions with shorter development cycles that support Intel's product and foundry ecosystem.

Work Model

This position follows a hybrid work model where employees split time between working on site at the assigned Intel location and working off site. Work model details and location arrangements may change based on business needs.

Intel follows responsible hiring practices and complies with Responsible Business Alliance (RBA) guidelines. Candidates are never required to pay recruitment or processing fees as part of the hiring process.