Mixed-Signal Verification Engineer at Cadence (Bangalore) | Full Time

About the Role

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. We are looking for a Mixed-Signal Systems and Verification Engineer to join our hands-on development team that fosters engineering excellence, creativity, and innovation.

Responsibilities

• Develop accurate and simulation-efficient analog behavioral models for analog/RF blocks in SystemVerilog.
• Verify that the behavior models are accurate representations of analog schematics.
• Integrate the models with RTL.
• Verify analog functionalities against design specifications using analog behavioral models, including coding test benches, test scenarios, and assertions.
• Document modeling and verification results for formal review.

Qualifications

• New graduates strongly encouraged to apply.
• Experience in developing and verifying real-numbered behavioral models in SystemVerilog.
• Understanding of SystemVerilog, RNM, UDN/UDT/UDR, wreal, and Verilog-AMS.
• Basic understanding of AMS blocks like filters, ADC, DAC, VCO, A/DPLL, SerDes, LNA, Mixer, etc.
• Working experience in low power architecture.
• Working experience in Cadence Virtuoso Schematic Composer and ADE.
• Experience with Analog Assertion Based Verification.
• Experience in TB development will be a strong plus.
• Experience in writing scripts in languages such as Perl or Python.
• Excellent teammate with excellent communication skills.
• Experience with FPGA prototyping is a plus.
• DSP experience is a huge plus.

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