Intel Hiring Mixed Signal Design Verification Engineer | Bangalore

Job Description

Intel is hiring a Mixed Signal Design Verification Engineer to support the functionality and quality verification of mixed signal logic components. The role involves developing and executing verification methodologies that help meet performance, power, and reliability targets for advanced technologies.

You will work closely with architects and designers to verify complex microarchitectural features in a fast-paced engineering environment.

Key Responsibilities

• Perform functional verification of mixed signal logic components, including analog behavioral modeling, to validate design specifications.
• Develop and execute IP verification plans, test benches, and verification environments for comprehensive coverage.
• Define and run system simulation models to verify functionality, evaluate power and timing, and identify potential issues.
• Debug and resolve pre-silicon issues, analyze failing tests, and implement corrective actions.
• Collaborate with digital and analog architects, RTL developers, and physical design teams to improve verification methodologies.
• Document test plans and participate in technical reviews with design and architecture teams.
• Maintain and enhance existing verification infrastructure and methodologies.

Qualifications

Minimum Qualifications

• Bachelor's or Master's degree in Electrical, Electronics, Computer Engineering, or a related field.
• 0-3 years of relevant industry experience with a Bachelor's degree, 1+ years with a Master's degree, or 0 years with a PhD.
• Proficiency in Verilog, SystemVerilog, and Universal Verification Methodology (UVM).
• Experience developing verification environments, test plans, and verification strategies.
• Hands-on exposure to simulation and debugging tools such as VCS and Verdi.
• Ability to analyze and debug RTL designs and verification challenges.

Preferred Qualifications

• Knowledge of low-power design techniques including UPF and clock gating.
• Familiarity with multiple clock domain designs and state machine concepts.
• Understanding of BFMs, checkers, coding coverage metrics, assertions, and formal verification.
• Knowledge of scripting languages such as Python, Perl, or Make.
• Awareness of methodologies including AVM, RVM, eRM, and UVM.
• Exposure to IO design and validation methodologies for analog, digital, and mixed-signal circuits.
• Familiarity with protocols such as PCI-Express, USB, Display Port, Ethernet, DDR, AMBA, JTAG, and PIPE.

This position follows Intel's hybrid work model, allowing a mix of on-site and off-site work.