Intel Hiring Analog Layout Design Engineer in Bangalore

Job Description

Intel is looking for an entry level Analog Layout Engineer to support analog and mixed signal IP development for a time bound assignment. The role involves working as an individual contributor under the guidance of senior layout and circuit designers, performing custom layout implementation and physical verification tasks for analog blocks used in SoC and IP designs.

Key Responsibilities

• Perform analog and custom layout design for assigned blocks under supervision.
• Implement layouts using tools such as Virtuoso or Custom Compiler, or similar platforms.
• Execute and debug physical verification checks including DRC, LVS, density, and reliability validations.
• Conduct EM/IR analysis using tools such as RedHawk or Totem.
• Support ESD and latch-up checks when required.
• Follow layout constraints provided by circuit designers and layout leads.
• Assist with layout iterations, engineering change orders (ECOs), and signoff closure activities.
• Follow established methodologies, checklists, and quality standards.
• Document layout issues and participate in reviews with senior engineers.

Qualifications

• Bachelor's degree (B.Tech) in Electrical Engineering, Electronics Engineering, or a related field.
• 0 to 2 years of experience or strong academic exposure in analog or custom layout design.
• Basic knowledge of analog layout practices and device matching concepts.
• Understanding of layout versus schematic consistency.
• Awareness of reliability and manufacturability considerations.
• Familiarity with custom layout tools and physical verification workflows.
• Ability to work independently while receiving technical guidance.

Preferred Qualifications

• Hands on exposure to Virtuoso or Custom Compiler.
• Experience using Calibre or ICV for DRC, LVS, and density checks.
• Exposure to RedHawk or Totem for EM/IR analysis.
• Academic projects or internships related to analog or mixed signal design or layout.
• Understanding of basic analog circuits such as operational amplifiers, drivers, or IO cells.
• Exposure to scripting languages like SKILL, Tcl, or Python is beneficial.

Business Group

The Central Engineering Group (CEG) at Intel focuses on building scalable engineering solutions across three main areas: Product Enablement, Custom ASIC development, and Foundry Enablement. The organization delivers customer driven, end to end engineering solutions with short development cycles to support Intel's product and foundry businesses.