Intel Hiring DFT Design Engineer in Bangalore | VLSI Role

Job Description

In this position, you will apply Design for Test (DFT) methodologies to help ensure Intel products meet strict quality and testability standards. The role involves working with engineering teams to integrate DFT features into complex silicon designs and contribute to reliable manufacturing test strategies.

Key Responsibilities

• Integrate DFT blocks into functional IP and SoCs, supporting high quality integration across multiple engineering teams.
• Develop and deliver manufacturing test content for DFx features, including SCAN, MBIST, and BSCAN.

Qualifications

Minimum Qualifications

• Bachelor's or Master's degree in Electronics Engineering, Microelectronics, or a related discipline.
• 0 to 1+ years of experience working with basic DFT methodologies.
• Experience with electronic design automation tools such as Siemens Tessent and waveform viewers.
• Knowledge of scripting languages including Tcl, Perl, or Python.
• Understanding of digital design principles and DFT concepts such as JTAG, iJTAG, SCAN, MBIST, and BSCAN.
• Familiarity with VLSI design flows and development methodologies.

Preferred Qualifications

• Awareness of current industry trends and evolving DFT approaches.
• Ability to collaborate effectively with multidisciplinary teams.

Business Group

The Central Engineering Group (CEG) is Intel's data driven engineering organization focused on scalable solutions. It operates across Product Enablement, Custom ASIC, and Foundry Enablement, building IP, tools, and methodologies that support rapid development cycles and measurable business impact.