Synopsys Bengaluru Hiring ASIC Digital Design Engineer | Freshers

We Are

Synopsys is the leader in engineering solutions from silicon to systems, helping customers quickly innovate AI-powered products. We deliver silicon design, IP, simulation and analysis solutions, and design services. We work closely with customers across many industries to maximize their R&D capability and productivity.

You Are

You are an early-career engineer ready to make your mark in semiconductor design. Your academic work drew you to digital design that requires proof, not just simulation. When you see a spec, you think about corner cases and what could break.

You have written Verilog or SystemVerilog, debugged logic that did not behave as expected, and you are comfortable in a Unix terminal. Formal verification may be new to you, but its rigor makes sense. You learn by doing, ask questions when stuck, and you do not mind being the person who finds the bug everyone else missed.

What You'll Be Doing

• Learn the latest formal verification methodology from experts and apply it to live projects.
• Work with a team of seasoned FV engineers and carry out validation according to defined plans.
• Support quality improvements and share insights that help enhance verification tool capabilities.
• Write and refine assertions in SystemVerilog Assertions (SVA) to capture design intent and uncover edge-case failures.
• Script verification flows using Python, Perl, or Tcl to automate repetitive tasks and improve team productivity in Unix/Linux environments.

The Impact You Will Have

• Help catch critical design bugs before tapeout, which would otherwise cost months and millions to fix in silicon.
• Contribute to the quality and reliability of Synopsys IP and EDA tools that power semiconductor development across the industry.
• Accelerate verification closure on complex designs by applying formal methods that simulation alone cannot cover.
• Strengthen the formal verification methodology at Synopsys by bringing fresh perspectives and identifying gaps in existing flows.

Who You Are

• You can look at a block diagram or RTL code and start asking the right questions about what could go wrong, not just what is supposed to work.
• You are comfortable learning new tools and methodologies on the job. You read documentation, try things, and ask targeted questions when stuck.
• You communicate clearly when you find something, whether it is a bug, a coverage gap, or a script that is not working as it should.
• You are detail-oriented enough to track down a single-bit logic error in a complex design without losing sight of what the block is supposed to do.

The Team You'll Be Part Of

You will join a focused team at Synopsys dedicated to advancing formal verification methodologies and delivering proven IP and EDA solutions. You will collaborate with experienced formal verification and design experts who push the boundaries of what formal methods can achieve.

The team values rigorous thinking, continuous learning, and clear communication, and it supports your growth.

Rewards and Benefits

Synopsys offers a comprehensive range of health, wellness, and financial benefits. Total rewards include both monetary and non-monetary offerings. Your recruiter will share more details about the salary range and benefits during the hiring process.